IBM Declares Novel Development in 3D Wafer Stacking

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At this level we’re all accustomed to the worldwide chip scarcity. It’s affected each single business on the earth, it appears. Now IBM has provide you with a brand new solution to manufacture silicon wafers that it says may ease the pressure a bit. It partnered with Tokyo Electron (TEL) on creating a brand new methodology for stacking silicon wafers vertically. Though IBM’s most superior analysis node is at the moment 2nm, it doesn’t state which course of it’s utilizing for this system. It solely mentions it’s utilizing it to stack 300mm (12-inch) wafers.

IBM’s announcement claims it’s the primary of its type for a wafer of this dimension. The purpose is to advance Moore’s Legislation by making wafer stacking an easier course of. It will permit IBM so as to add extra transistors to a given quantity by way of stacking. It notes that historically 3D stacking has solely been utilized in “excessive finish operations” resembling with Excessive-Bandwidth Reminiscence (HBM). AMD has notably additionally accomplished it not too long ago with the L3 cache on its Ryzen 7 5800X3D CPU. It additionally was the primary GPU firm to employe HBM on a GPU with its Fiji and Fury households, again in 2015.

(Picture: IBM)

IBM’s new course of is actually a novel solution to be a part of silicon wafers collectively. Conventional chip-stacking requires through-silicon vias (TSVs) between the layers. This enables electrical energy to circulation upwards into the stack, and for each layers to work in tandem. This requires the bottom of the layer to be thinned to disclose the TSVs for the opposite layer to connect with them. The layers in a stack are very skinny, measuring lower than 100 microns. Because of their fragility, they require a provider wafer to help them.

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Sometimes these provider wafers are made from glass. The provider wafer is bonded to the wafer to ensure it may well undergo manufacturing with out being broken. As soon as it’s completed manufacturing, the provider is eliminated with a UV laser. In some instances a silicon provider can be utilized too, however separating it from the layer requires a mechanical drive. This may be harmful for the integrity of the wafer it’s purported to be defending. That is the place IBM’s new invention comes into play, because it’s found out a solution to debond two silicon wafers that’s clear to silicon. It has achieved this by utilizing an infrared laser to decouple the wafers.

It will permit two silicon wafers to be stacked with out using glass carriers. As an alternative manufactures can simply skip that step and go straight to silicon-to-silicon. IBM says along with simplifying the method by now not requiring this further step, there are different benefits as effectively. For example it says it would assist in eliminating software compatibility and chucking points, introduce fewer defects, and permit for inline testing of thinned wafers. These advantages will allow “superior chiplet manufacturing” in line with IBM. It additionally says its expertise can scale very effectively.

IBM and TEL have been engaged on this expertise since 2018, so it’s been within the hopper for a short time. This might be an important improvement for the business given the place issues are headed in silicon fabrication. As node sizes shrink right down to sub-2nm, packaging and stacking applied sciences will turn out to be an important benefit for firms trying to enhance efficiency when “transferring to a smaller node” is now not an choice.

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Intel is already trying to start superior 3D stacking with Meteor Lake, utilizing its Foveros expertise. AMD is manner forward of the sport on that entrance, as talked about beforehand. Nonetheless, thus far it’s solely stacking L3 cache on its CPUs with Zen 3. Nonetheless, there are rumors it would repeat that with Zen 4 as effectively with so-called Raphael-X merchandise. It stays unclear if stacking can even be employed in its upcoming RDNA3 GPUs.

IBM says it’s constructed a beta tooling facility in Albany, NY to work on its new expertise. Sooner or later it will likely be increasing its work. Its purpose is to ultimately create a full 3D chip stack utilizing this expertise. The corporate says this development will assist with provide chain points, whereas additionally permitting for efficiency advantages too. “We hope our work will assist minimize down on the variety of merchandise wanted within the semiconductor provide chain, whereas additionally serving to drive processing energy enhancements for years to come back,” it said.

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