At this level we’re all conversant in the worldwide chip scarcity. It’s affected each single business on the earth, it appears. Now IBM has give you a brand new option to manufacture silicon wafers that it says may ease the pressure a bit. It partnered with Tokyo Electron (TEL) on creating a brand new technique for stacking silicon wafers vertically. Though IBM’s most superior analysis node is at present 2nm, it doesn’t state which course of it’s utilizing for this method. It solely mentions it’s utilizing it to stack 300mm (12-inch) wafers.
IBM’s announcement claims it’s the primary of its variety for a wafer of this dimension. The aim is to advance Moore’s Regulation by making wafer stacking an easier course of. This may permit IBM so as to add extra transistors to a given quantity through stacking. It notes that historically 3D stacking has solely been utilized in “excessive finish operations” similar to with Excessive-Bandwidth Reminiscence (HBM). AMD has notably additionally executed it lately with the L3 cache on its Ryzen 7 5800X3D CPU. It additionally was the primary GPU firm to employe HBM on a GPU with its Fiji and Fury households, again in 2015.
IBM’s new course of is basically a novel option to be part of silicon wafers collectively. Conventional chip-stacking requires through-silicon vias (TSVs) between the layers. This permits electrical energy to circulation upwards into the stack, and for each layers to work in tandem. This requires the bottom of the layer to be thinned to disclose the TSVs for the opposite layer to connect with them. The layers in a stack are very skinny, measuring lower than 100 microns. Resulting from their fragility, they require a service wafer to help them.
Sometimes these service wafers are fabricated from glass. The service wafer is bonded to the wafer to ensure it may well undergo manufacturing with out being broken. As soon as it’s completed manufacturing, the service is eliminated with a UV laser. In some circumstances a silicon service can be utilized too, however separating it from the layer requires a mechanical drive. This may be harmful for the integrity of the wafer it’s imagined to be defending. That is the place IBM’s new invention comes into play, because it’s found out a option to debond two silicon wafers that’s clear to silicon. It has achieved this by utilizing an infrared laser to decouple the wafers.
This may permit two silicon wafers to be stacked with out using glass carriers. As an alternative manufactures can simply skip that step and go straight to silicon-to-silicon. IBM says along with simplifying the method by now not requiring this additional step, there are different benefits as effectively. For example it says it is going to assist in eliminating software compatibility and chucking points, introduce fewer defects, and permit for inline testing of thinned wafers. These advantages will allow “superior chiplet manufacturing” in line with IBM. It additionally says its know-how can scale very effectively.
IBM and TEL have been engaged on this know-how since 2018, so it’s been within the hopper for a short time. This could possibly be a vital growth for the business given the place issues are headed in silicon fabrication. As node sizes shrink right down to sub-2nm, packaging and stacking applied sciences will turn into a vital benefit for firms seeking to improve efficiency when “shifting to a smaller node” is now not an choice.
Intel is already seeking to start superior 3D stacking with Meteor Lake, utilizing its Foveros know-how. AMD is manner forward of the sport on that entrance, as talked about beforehand. Nonetheless, up to now it’s solely stacking L3 cache on its CPUs with Zen 3. Nonetheless, there are rumors it is going to repeat that with Zen 4 as effectively with so-called Raphael-X merchandise. It stays unclear if stacking will even be employed in its upcoming RDNA3 GPUs.
IBM says it’s constructed a beta tooling facility in Albany, NY to work on its new know-how. Sooner or later will probably be increasing its work. Its aim is to ultimately create a full 3D chip stack utilizing this know-how. The corporate says this development will assist with provide chain points, whereas additionally permitting for efficiency advantages too. “We hope our work will assist reduce down on the variety of merchandise wanted within the semiconductor provide chain, whereas additionally serving to drive processing energy enhancements for years to come back,” it acknowledged.