Intel 4 is a Main Step on Intel’s Path Again to Semiconductor Dominance

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At ISC 22 final week, Intel shared new particulars on its subsequent main node, dubbed Intel 4. Earlier than Intel rejigged its course of node naming methodology, we’d’ve referred to this as 7nm. Intel 4 is ready to be a significant step ahead for the corporate and it appears to be like to be tailor-made in the direction of Intel’s strongest high-performance merchandise. It’s going to should be. Intel 4 is a important step for the corporate because it seeks to reclaim its manufacturing throne.

Transferring Previous 10nm

It isn’t an exaggeration to say that Intel’s 10nm manufacturing miss had a huge effect on each the corporate and the general state of competitors within the x86 market. Intel introduced 22nm and FinFETs to market forward of all of its opponents, however then needed to delay its 14nm node to repair sure issues. With 10nm, the corporate promised a triumphant return to kind. Even after it hit delays, it adopted up by promising aggressive function dimension shrinks and total enhancements that might maintain Intel in a management place in cellular 10nm, whereas setting the corporate up for long-term desktop and server efficiency success as soon as a third-generation “10nm++” was prepared. 14nm could be improved for a number of generations to cowl the hole.

This slide grew to become a bit notorious because the “+” variations of 14nm started to pile up, with no desktop 10nm in sight.

Issues didn’t play out this fashion, and Intel’s 10nm remained mired in problem for a number of years. Its first elements — based mostly on the Cannon Lake microarchitecture — solely shipped in a dual-core configuration with low clocks and no useful GPU. It took Intel years to repair 10nm and a number of other successive generations of cellular product (Ice Lake, Tiger Lake). Intel did lastly transfer its desktop chips over to Intel 7 (aka third-generation 10nm) with Alder Lake final 12 months, however the firm is a number of years delayed and has brazenly acknowledged that 10nm didn’t meet its preliminary expectations.

We’re largely right here as we speak to speak about Intel 4, however the design of this node gives a couple of hints as to what went mistaken again on 10nm. When requested about this, Intel was frank, acknowledging that it had tried to do an excessive amount of at 10nm. Whereas the corporate didn’t go into an excessive amount of element, Intel’s dialogue of its next-generation course of node gives a couple of new hints as to what went mistaken.

Contact Over Energetic Gate

COAG stands for “Contact Over Energetic Gate,” however given the issues Intel bumped into at 10nm, it might’ve stood for “Cobalt Provides Terrible Positive factors,” or possibly “CObalt: Really Rubbish.” Intel deployed cobalt extensively all through 10nm, utilizing it for contacts, metallization, and vias for each M0 and M1. When it introduced 10nm, Intel claimed cobalt would scale back contact line resistance by 60 % in comparison with tungsten. Resistance to electromigration harm was stated to extend by a number of orders of magnitude.

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Sadly, cobalt is taken into account fairly troublesome to work with, and manufacturing issues with the fabric are regarded as no less than partly liable for Intel’s manufacturing delays at 10nm. RealWorldTech has a superb writeup of Intel 4 for anybody who desires the deepest technical dive, so I’m going to allow them to clarify this bit:

At smaller geometries, the contact layer is more and more difficult resulting from alignment necessities, resistance, and potential capacitance between the contact and gate. A typical contact gap will likely be 20nm or much less in diameter. Intel explicitly indicated that the metallic has reverted from cobalt again to pure tungsten and {that a} single damascene course of is used to kind the contacts separate from the M0 layers. This can be very seemingly that the contacts are printed utilizing EUV [Extreme UltraViolet]. The change from cobalt again to tungsten additionally implies that the contacts use a unique course of stream that will increase the amount of tungsten which seemingly improves the contact resistance in comparison with the cobalt-based Intel 7.

Picture by RealWorldTech. Intel 7 (aka 10nm) is on the far left.

The truth that Intel made a giant deal concerning the change from copper to cobalt within the transfer from 14nm to 10nm, solely to show and head again to enhanced copper with Intel 4 (unique 7nm) factors to issues with cobalt on the manufacturing stage. Cobalt has a lot larger resistance than copper and this might partly clarify the low frequencies Intel initially supplied with Cannon Lake and Ice Lake. The corporate was clearly in a position to enhance the issue in later 10nm / Intel 7 {hardware}, as a result of Tiger Lake and Alder Lake have each hit larger clocks than Ice Lake, however Intel nonetheless isn’t sticking with its earlier method because it shrinks the node.

What’s New in Intel 4

Intel 4 is a full node shrink relative to Intel 7, with an estimated 20 % efficiency enchancment in the identical energy envelope, or a 40 % discount in energy on the identical clock. It’s the primary full node shrink that Intel has introduced because it re-launched its efforts to function a consumer foundry for different chip designers, however the firm doesn’t anticipate its new prospects to deploy Intel 4, although it burdened they are going to be capable of use it in the event that they wish to. As an alternative, Intel believes its future modern foundry prospects will largely goal Intel 3 when that course of is obtainable.

One cause why Intel’s foundry prospects would possibly favor Intel 3 over Intel 4 is as a result of Intel 4 is optimized for high-performance silicon. Most of TSMC’s prospects don’t prioritize uncooked efficiency the way in which Intel, Nvidia, AMD, IBM, and a handful of different firms do. Many chip designs are optimized for very excessive transistor densities and/or low energy versus excessive efficiency.

Knowledge and slide by Intel

When a foundry deploys a node for a variety of consumers, it is going to create design libraries for each high-performance and high-density merchandise. On this case, Intel has deployed excessive efficiency libraries appropriate for constructing CPUs on Intel 4 and plans to introduce excessive density libraries appropriate for GPUs and different ASICs on Intel 3. This suggests that Intel will proceed to faucet TSMC for its non-CPU and chipset manufacturing for the foreseeable future.

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Intel will introduce EUV into manufacturing with the Intel 4 course of earlier than deepening its use of the expertise with Intel 3. Intel is the final of the top-tier semiconductor foundries to undertake EUV in quantity manufacturing, regardless of being one of many first corporations to name for its growth 20 years in the past. EUV is a alternative for the older 193nm “DUV” (Deep UltraViolet) lithography and is used to print smaller options and scale back the variety of steps required within the chip manufacturing course of.

Knowledge and slide by Intel

In line with Intel, the variety of masks it wanted to make use of per CPU would have jumped 30 % from Intel 7 to Intel 4 with out EUV. As an alternative, the variety of masks required for Intel 4 dropped by 20 %. Whole course of steps decreased by 5 %. Like TSMC, Intel’s preliminary adoption of EUV will likely be restricted. The corporate is reportedly utilizing EUV for contacts, however solely sure metallic layers and vias. TSMC and Samsung each use EUV for contacts, vias, and metallic layers. Intel is predicted to widen its adoption of EUV with Intel 3, so this hole will slender over time. RWT notes that Intel continues to be utilizing SAQP (aka quad patterning) for sure metallic layers, which means the older expertise continues to be extra economical or efficient than EUV in sure circumstances.

What Does All This Imply For Intel?

Intel 4 is explicitly designed for top efficiency microprocessors. When Pat Gelsinger got here again to Intel, he pledged that the corporate would refocus on excessive efficiency microprocessors and on re-achieving market technical management. Intel 4 is meant to advance that objective and can energy upcoming CPU tiles like Meteor Lake.

Introducing EUV is a giant step for each producer. Intel is selecting to maneuver extra cautiously with the expertise. On this, it’s echoing one thing extra like TSMC’s path to EUV than Samsung’s. TSMC launched EUV in restricted capability at 7nm after which improved its 5nm utilization. Samsung, in distinction, went all-in on EUV from 7nm ahead. Samsung, nonetheless, has additionally been fighting yield issues for years now. Yields on its 3nm GAA (Gate-all-around) course of had been reportedly within the 10-20 % vary earlier this 12 months, whereas its 4nm course of is just yielding at 35 %. Yields on early nodes are all the time poor initially, however these numbers are going to pull on Samsung’s efforts to win prospects for its modern manufacturing.

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By treating Intel 4 as the muse Intel 3 will construct on, Intel splits its EUV transition throughout two nodes and simplifies its personal studying curve. EUV and Intel 4 will ramp at Intel’s Hillsboro fab first earlier than being duplicated at Leixlip. Ramping manufacturing in a second fab presents its personal challenges — that is why Intel makes use of its “Copy Precisely” method for fab design — however Intel will likely be its personal buyer for these elements through the preliminary build-out. It needs to be simpler to maneuver from Intel 4 to Intel 3 than to leap straight from Intel 7 (non-EUV) to Intel 3 (EUV) with no step within the center.

I speak rather a lot about how foundry manufacturing is an extended sport, and Intel’s 10nm saga and potential restoration present that development nicely. When Intel launched 22nm, it beat the remainder of the world to FinFETs by a number of years. It took Intel years to repair its 10nm course of, however the firm was in a position to resolve its issues nicely sufficient to ultimately transition its excessive efficiency microprocessors over to the node. As an alternative of making an attempt to duplicate its “Every thing + Kitchen Sink” method to 10nm, Intel will cut up the enhancements and give attention to excessive efficiency elements first, with excessive density libraries, extra EUV integration, and help for a broader vary of consumers all arriving with Intel 3.

Intel’s issues at 10nm are simply the largest “miss” the corporate has suffered in many years, however Intel was by no means in any monetary hazard from its 14nm hangover. I wouldn’t guess in opposition to Intel competing once more for management in semiconductor manufacturing for a similar cause I wouldn’t have guess in opposition to Intel 17 years in the past, when the Athlon 64 X2 was an ascending star and Intel’s dual-core Pentium D CPUs had been sucking wind. Intel’s dual-core Pentium D CPUs (codenamed Smithfield) would ultimately have a little bit of revenge on the remainder of the market as late-game star overclockers, however whereas Prescott-derived cores made the corporate some huge cash, they did nothing for its popularity. Hypothesis that AMD would bankrupt Intel reached a fever pitch amongst lovers from 2004 – early 2006. Then Intel launched the Core 2 Duo “Conroe,” and spent the following 11 years because the unchallenged king of high-end x86 efficiency.

Hitting Intel is rather a lot like hitting a rubber wall with a hammer. Denting it’s simple. Inflicting significant, long-term harm? That’s harder, particularly if the “harm” quantities to little greater than “Making modestly much less web revenue on an annual foundation.” It’s a lot too early to foretell whether or not Intel will reach retaking the semiconductor efficiency throne, however the firm has laid out a believable path to get itself there by emphasizing its historic engineering and management function within the trade. TSMC shouldn’t be quaking in its boots, however it shouldn’t be ignoring the long-term menace, both.

Function picture is a check wafer for Meteor Lake, constructed on Intel 4. Picture by Intel.

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