At this week’s Intel Imaginative and prescient occasion the corporate proudly displayed a few of its next-gen silicon. Though its present and subsequent technology CPUs characteristic a “hybrid” design, the corporate is shifting to tile-based designs after that. Intel’s tiles are much like chiplets, although there are some organizational variations when it comes to what Intel intends to do with tiles versus how AMD has deployed chiplets. Intel’s next-generation Meteor Lake will nonetheless use hybrid cores, however the chip will discipline a number of tiles.
The CPUs Intel displayed are slated for 2023 and past, offering a uncommon glimpse into the corporate’s future merchandise.
As a fast refresher, Intel is planning to launch Raptor Lake this yr because the successor to Alder Lake. Will probably be an optimized improve to the structure utilizing the identical Intel 7 course of. That is much like Intel’s Tick-Tock technique from yesteryear, the place it introduces a CPU on a smaller node, then refines it. After Raptor Lake comes Meteor Lake, which will likely be a watershed product for Intel. Will probably be the corporate’s first tile-based CPU, using each Intel and TSMC silicon. It’s exceptional in that it’ll mix three completely different manufacturing nodes on one package deal. It is going to characteristic 4 tiles, with the I/O and CPU tiles made on Intel 4 (previously 7nm). The GPU will likely be a TSMC 3nm half with the SoC being a TSMC N4/N5 half, in line with Videocardz.
It’ll be the primary shopper CPU to make use of Foveros and Embedded Multi-Die Interconnect Bridges (EMIB) to attach tiles each vertically and laterally. Intel displayed two variations of Meteor Lake: customary and high-density packaging. The usual packaging seems to be a cellular kind issue, whereas the high-density seems extra like a conventional desktop CPU. That is the principle profit to this strategy; it will probably regulate an present configuration for various energy necessities. Japanese website PC Watch was on-hand for the occasion, and took loads of pictures.
The corporate additionally confirmed off its massive boy; Ponte Vecchio. This huge chip packs over 100 billion transistors and makes use of EMIB and Foveros to attach a whopping 47 tiles in a single package deal. Like Meteor Lake, tiles are related each vertically and laterally. The chip was designed for the Division of Power’s Aurora Exascale supercomputer, however can even be bought to clients working within the HPC and AI fields as effectively. This insanely complicated chip will characteristic reminiscence cloth able to over 5TB/s of bandwidth.
Intel appears to be holding tempo with its lofty aim of advancing 5 nodes in 4 years. These nodes are Intel 7, Intel 4, Intel 3, 20A, and 18A. This corresponds roughly to a refined Intel 10nm, Intel 7nm, and a future Intel 5nm underneath the outdated node naming regime. Displaying off its chips like this can be a method for it to reassure the general public, and traders, that it’s nonetheless making progress. Intel’s CEO additionally lately flashed an 18A SRAM wafer at an investor assembly in February and stated it’s at the moment six months forward of schedule.