At its Monetary Analyst Day in the present day, AMD shared its upcoming CPU roadmap and related node transition plans for the following few years. Whereas the corporate has rather a lot to say about varied facets of its enterprise, it’s the Zen 4 CPU bulletins we wish to contact on in the present day. Zen 4 is seemingly a a lot bigger enchancment over Zen 3 than AMD had beforehand disclosed.
The Zen “4C” core referenced right here is Bergamo, AMD’s tweaked CPU design with assist as much as 128 cores. The usual Zen 4 core, Genoa, tops out at 96 cores. AMD is planning to fabricate chips with TSMC’s 4nm node sooner or later, although it hasn’t specified which CPUs will use it. In line with TSMC, 4nm is an enhanced 5nm node with some small space financial savings (~6 p.c) however decrease course of complexity “through masks discount” and higher efficiency/energy “via system and BEOL enhancement.” BEOL stands for Again Finish of Line — it’s a reference to a selected step within the IC fabrication course of, the place interconnects are laid down and metallic layers are deposited. AMD hasn’t made a really huge deal over its use of 6nm and it may not make a lot noise over 4nm, both.
One factor AMD confirmed in the present day is that V-Cache will seem on future Zen 4 consumer desktop CPUs, although the corporate avoided saying a lot about what number of SKUs may supply the additional L3. V-Cache makes the Ryzen 7 5800X3D a very attention-grabbing improve choice for older Ryzen house owners with slower DRAM, as we lately mentioned. AMD didn’t give a timeline for V-Cache introduction with Zen 4, nevertheless, so it could not launch when the remainder of the chips debut.
Zen 4 Hits the Fuel on Frequency
With regards to Zen 4, it seems AMD may need been sandbagging a bit at Computex. Again then it stated its upcoming structure will supply ~>15 p.c single-threaded efficiency uplift over Zen 3, however that was the one quantity it threw out. Now AMD says it’s higher than 35 p.c enhance for Zen 4 over Zen 3, although it’s not clear if that determine refers to single-threaded efficiency, multi-threaded efficiency, or a mixture between the 2. The corporate additionally predicts that Zen 2 will supply a 25 p.c efficiency per watt enchancment over Zen 3.
Proper now it appears to be like as if most of those good points are more likely to come from clock velocity. AMD lately confirmed a 16-core CPU working at 5.5GHz and claimed nothing past an off-the-shelf AIO cooler was required to hit these clocks. If we assume a all-core most frequency enhance from 4.5GHz to five.5GHz — which is actually huge — AMD would wish to supply roughly 1.1x further IPC to hit a 1.35x efficiency enchancment. AMD has raised its CPU TDP to 170W and most socket energy to 230W, so the corporate apparently plans to offer Zen 4 a little bit extra room to breathe in 2022. Mark Papermaster claimed an 8-10 p.c acquire in IPC from stage in the present day, so the maths checks out. If something, a 1.15x efficiency enchancment for single-thread appears low.
Hitting frequencies like this whereas concurrently enhancing IPC and stopping efficiency per watt from falling implies TSMC’s 5nm is hitting clock frequencies Intel may properly envy. We’ve requested AMD for extra particulars on the way it improved its frequencies so dramatically however the firm isn’t prepared to speak in regards to the structure at that degree of element but.
Hitting these efficiency targets would greater than shut the hole with Alder Lake — it will additionally put the corporate on a stable footing in opposition to Intel’s upcoming thirteenth Gen platform, codenamed Meteor Lake. The implication of AMD’s Monetary Analyst Day is that Intel can’t depend on a simple win in opposition to its smaller rival. All producer information must be taken with a grain of salt, and AMD is not any exception, however AMD’s CPU enterprise has nailed its projections for years now. A 1.35x efficiency enhance is bigger than anticipated, however AMD’s publicly demonstrated clock speeds recommend a path for getting there.
Managing Editor Joel Hruska contributed to this text.